| Description | This article describes details about port combination link aggregation group (LAG) support for FortiGate-600F and 601F hardware platforms. |
| Scope | Any supported version of FortiGate. |
| Solution |
Both the FortiGate-600F and 601F platforms support combining ultra-low latency (ULL) ports (X5 to X8) and non-ULL ports (X1 to X4) as members in the same LAG. ULL ports (X5 to X8) are directly connected to NP7, while non-ULL ports (X1 to X4) are connected to NP7 through ISF.
Note: If the device has multiple NP7 chips, all Ports defined in the LAG need to connect to the same NP7 chip: FortiGate NP7 architectures.
See the diagram below for the locations of these ports:
This diagram is based on the one available from the hardware acceleration fast path architecture section of the documentation: FortiGate 600F and 601F fast path architecture.
Note: The above setup is also valid for the FortiGate-400F, 401F, 900G, and 901G hardware platforms.
For more information, find the below document: FortiGate 400F and 401F fast path architecture. |
