FortiGate
FortiGate Next Generation Firewall utilizes purpose-built security processors and threat intelligence security services from FortiGuard labs to deliver top-rated protection and high performance, including encrypted traffic.
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Article Id 190190

Description

 

This article describes interface error counters.

 

Scope

 

  • All FortiGate units.
  • The output of the diagnose command may vary depending on the interface driver.

 

Solution

 

The counters and their meaning describe what can be seen when using the CLI command:

 

diag hardware deviceinfo nic interface.

 

Rx_Errors = rx error count The bad frame was marked as an error by PHY.
Rx_CRC_Errors + Rx_Length_Errors + Rx_Align_Errors Valid in 10/100M mode.
Rx_CRC_Errors
Frame CRC errors can be caused by a number of factors. Typically, they are caused by either faulty cabling, or as the result of a collision
Rx_Dropped Running out of buffer space. A newer error is rx_no_buffer_count.
Rx_Missed_Errors

Equals Rx_FIFO_Errors + CEXTERR (Carrier Extension Error Count). Only valid in 1000M mode, which is marked by PHY.

Tx_Errors=Tx_Aborted_Errors ECOL, Excessive Collisions Count. Valid in half-duplex mode.
Tx_Window_Errors LATECOL, Late Collisions Count. Late collisions are collisions that occur after 64-byte time into the transmission of the packet while working at 10-100 Mb/s data rate, and 512 byte time into the transmission of the packet while working at the 1000 Mb/s data rate. This registers only increments if transmits are enabled and the device is in half-duplex mode.
Rx_Dropped See RX error.
Tx_Dropped Number of dropped packets.
Collisions Total number of collisions experienced by the transmitter. Valid in half-duplex mode.
Rx_Over_Errors Receive FIFO overflow event counter.
Rx_CRC_Errors Frame CRC errors can be caused by a number of factors. Typically, they are caused by either faulty cabling, or as the result of a collision
Rx_Frame_Errors Same as Rx_Align_Errors. This error is only valid in 10/100M mode.
Rx_FIFO_Errors Same as Rx_Missed_Errors; missed packet count.
Tx_Aborted_Errors ECOL - Excessive Collisions Count. Only valid in half-duplex mode.
Tx_Carrier_Errors The PHY should assert the internal carrier sense signal during every transmission. Failure to do so may indicate that the link has failed, or the PHY has an incorrect link configuration. This register only increments if transmits are enabled. This register is not valid in internal SerDes1 mode (TBI mode for the 82544GC/EI), and is only valid when the Ethernet controller is operating at full duplex.
Rx_Length_Errors Transmission length error.
Tx_FIFO_Errors

 Number of Frame transmission errors due to underflow.

Tx_Heartbeat_Errors

Number of heartbeat errors.

Tx_Window_Errors

LATECOL - Late Collisions Count.

Tx_Single_Collision_Frames

Counts the number of times that a successfully transmitted packet encountered a single collision. The value only increments, if transmits, are enabled and the Ethernet controller is in half-duplex mode.

Tx_Multiple_Collision_Frames

Multiple Collision Count, counts the number of times that a transmit encountered more than one collision but less than 16. The value only increments, if transmits, are enabled and the Ethernet controller is in half-duplex mode.

Tx_Deferred

Counts defer events. A defer event occurs when the transmitter cannot immediately send a packet due to the medium being busy either because another device is transmitting, the IPG timer has not expired, half-duplex deferral events, reception of XOFF frames, or the link is not up. This register only increments if transmits are enabled. This counter does not increment for streaming transmits that are deferred due to TX IPG.

Rx_Frame_Too_Longs

Rx frame oversize.

Rx_Frame_Too_Shorts

Rx frames are too short.

Rx_Align_Errors This error is only valid in 10/100M mode.
Symbol Error Count SYMERRS - Counts the number of symbol errors between reads. The count increases for every bad symbol received, whether or not a packet is currently being received and whether or not the link is up. this register only increments in internal SerDes mode.